| Architecture And Optimization Of Associative Memories Used For The Implementation Of Logic Functions Based On Nanoelectronic 1s1r Cells | 0 | 0.34 | 2018 |
| Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup. | 0 | 0.34 | 2017 |
| Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems. | 3 | 0.39 | 2017 |
| Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells | 0 | 0.34 | 2017 |
| Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency. | 0 | 0.34 | 2017 |
| A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects | 0 | 0.34 | 2016 |
| A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency | 1 | 0.36 | 2016 |
| On The Use Of Analytical Techniques For Reliability Analysis In Presence Of Hardware-Induced Errors | 0 | 0.34 | 2015 |
| Design and synthesis of reconfigurable control-flow structures for CGRA | 1 | 0.36 | 2015 |
| F3: Adaptive design techniques for energy efficiency | 0 | 0.34 | 2014 |
| Limits of gate-level power estimation considering real delay effects and glitches | 2 | 0.47 | 2014 |
| Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit | 0 | 0.34 | 2014 |
| Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption | 1 | 0.38 | 2014 |
| Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays | 1 | 0.43 | 2013 |
| Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation | 1 | 0.45 | 2013 |
| An accurate power estimation model for low-power hierarchical-architecture SRAMs | 1 | 0.37 | 2013 |
| High-level modeling and synthesis for embedded FPGAs | 3 | 0.40 | 2013 |
| Quantitative Optimization And Early Cost Estimation Of Low-Power Hierarchical-Architecture Srams Based On Accurate Cost Models | 0 | 0.34 | 2013 |
| Cross-layer optimization of QRD accelerators | 4 | 0.45 | 2013 |
| Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits | 1 | 0.43 | 2013 |
| An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks | 3 | 0.68 | 2012 |
| A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights. | 0 | 0.34 | 2012 |
| Efficient VLSI architectures of QPP interleavers for LTE turbo decoders | 3 | 0.40 | 2012 |
| A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars | 5 | 0.77 | 2012 |
| A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations | 1 | 0.36 | 2012 |
| Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme | 3 | 0.53 | 2012 |
| Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits | 9 | 0.88 | 2012 |
| Statistical modeling of reliability in logic devices. | 1 | 0.35 | 2011 |
| Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization | 3 | 0.66 | 2011 |
| Area- and energy-efficient high-throughput LDPC decoders with low block latency | 2 | 0.41 | 2011 |
| Interconnect routing of embedded FPGAs using standard VLSI routing tools | 1 | 0.37 | 2010 |
| Potential Of Using Block Floating Point Arithmetic In Asip-Based Gnss-Receivers | 1 | 0.43 | 2010 |
| LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates | 8 | 0.77 | 2010 |
| A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point | 0 | 0.34 | 2010 |
| Adaptive kernel algorithm for FPGA-based speckle reduction | 0 | 0.34 | 2008 |
| Design flow for embedded FPGAs based on a flexible architecture template | 11 | 0.68 | 2008 |
| ASIP-eFPGA Architecture for Multioperable GNSS Receivers | 1 | 0.37 | 2008 |
| Application-specific reconfigurable processors | 0 | 0.34 | 2008 |
| Design of a Pareto-optimization environment and its application to motion estimation. | 0 | 0.34 | 2008 |
| Programmable Architectures for Realtime Music Decompression | 0 | 0.34 | 2007 |
| Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory | 28 | 4.29 | 2007 |
| Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers | 2 | 0.54 | 2007 |
| Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform | 4 | 0.43 | 2007 |
| Hybrid functional and instruction level power modeling for embedded processors | 5 | 0.64 | 2006 |
| A scalable packet sorting circuit for high-speed WFQ packet scheduling | 5 | 0.43 | 2006 |
| Error-tolerant FIR filters based on low-cost residue codes | 3 | 0.72 | 2005 |
| A Parametrizable Low-Power High-Throughput Turbo-Decoder | 24 | 1.33 | 2005 |
| Object based refinement of motion vector fields applying probabilistic homogenization rules | 9 | 0.98 | 2002 |
| A Hardware Implementation For Approximate Text Search In Multimedia Applications | 2 | 0.53 | 2000 |
| Verbesserung der Dynamik und Ortsauflösung in der Ultraschalldiagnostik durch die Kombination kodierter Anregung und tiefenangepaßter Mismatched-Filterung | 0 | 0.34 | 1998 |
