Search Limit
Architecture And Optimization Of Associative Memories Used For The Implementation Of Logic Functions Based On Nanoelectronic 1s1r Cells00.342018
Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup.00.342017
Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems.30.392017
Mixing circuit based on neural associative memories and nanoelectronic 1S1R cells00.342017
Optimal Datapath Widths Within Turbo and Viterbi Decoders for High Area- and Energy-Efficiency.00.342017
A framework for analyzing the propagation of hardware-induced errors in non-recursive LTI blocks with finite wordlength effects00.342016
A Family of Modular QRD-Accelerator Architectures and Circuits Cross-Layer Optimized for High Area- and Energy-Efficiency10.362016
On The Use Of Analytical Techniques For Reliability Analysis In Presence Of Hardware-Induced Errors00.342015
Design and synthesis of reconfigurable control-flow structures for CGRA10.362015
F3: Adaptive design techniques for energy efficiency00.342014
Limits of gate-level power estimation considering real delay effects and glitches20.472014
Variability analysis of a hybrid CMOS/RS nanoelectronic calibration circuit00.342014
Statistical Modeling of Glitching Effects in Estimation of Dynamic Power Consumption10.382014
Analysis of the area-delay performance of hybrid nanoelectronic memory cores used in field programmable gate arrays10.432013
Modeling variability and irreproducibility of nanoelectronic resistive switches for circuit simulation10.452013
An accurate power estimation model for low-power hierarchical-architecture SRAMs10.372013
High-level modeling and synthesis for embedded FPGAs30.402013
Quantitative Optimization And Early Cost Estimation Of Low-Power Hierarchical-Architecture Srams Based On Accurate Cost Models00.342013
Cross-layer optimization of QRD accelerators40.452013
Variability evaluation of feedback circuits used in nanoelectronic Memristive/CMOS circuits10.432013
An approach for quantitative optimization of highly efficient dedicated CORDIC macros as SoC building blocks30.682012
A hybrid CMOS/memristive nanoelectronic circuit for programming synaptic weights.00.342012
Efficient VLSI architectures of QPP interleavers for LTE turbo decoders30.402012
A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars50.772012
A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations10.362012
Low power 6T-SRAM with tree address decoder using a new equalizer precharge scheme30.532012
Limits of writing multivalued resistances in passive nanoelectronic crossbars used in neuromorphic circuits90.882012
Statistical modeling of reliability in logic devices.10.352011
Sensitivity of neuromorphic circuits using nanoelectronic resistive switches to pulse synchronization30.662011
Area- and energy-efficient high-throughput LDPC decoders with low block latency20.412011
Interconnect routing of embedded FPGAs using standard VLSI routing tools10.372010
Potential Of Using Block Floating Point Arithmetic In Asip-Based Gnss-Receivers10.432010
LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates80.772010
A digit-set-interleaved radix-8 division/square root kernel for double-precision floating point00.342010
Adaptive kernel algorithm for FPGA-based speckle reduction00.342008
Design flow for embedded FPGAs based on a flexible architecture template110.682008
ASIP-eFPGA Architecture for Multioperable GNSS Receivers10.372008
Application-specific reconfigurable processors00.342008
Design of a Pareto-optimization environment and its application to motion estimation.00.342008
Programmable Architectures for Realtime Music Decompression00.342007
Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory284.292007
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers20.542007
Performance and Power Analysis of Parallelized Implementations on an MPCore Multiprocessor Platform40.432007
Hybrid functional and instruction level power modeling for embedded processors50.642006
A scalable packet sorting circuit for high-speed WFQ packet scheduling50.432006
Error-tolerant FIR filters based on low-cost residue codes30.722005
A Parametrizable Low-Power High-Throughput Turbo-Decoder241.332005
Object based refinement of motion vector fields applying probabilistic homogenization rules90.982002
A Hardware Implementation For Approximate Text Search In Multimedia Applications20.532000
Verbesserung der Dynamik und Ortsauflösung in der Ultraschalldiagnostik durch die Kombination kodierter Anregung und tiefenangepaßter Mismatched-Filterung00.341998
  • 1
  • 2