Name
Abstract | ||
|---|---|---|
To reduce both dynamic and standby power dissipation, a new 6T-based SRAM architecture is proposed. It is partitioned into an optimal number of hierarchical sub-blocks, which are selectively activated by a novel tree address decoder. Also, a new equalizer precharge scheme with reduced leakage paths is presented. Low standby power and stable access are achieved with back-biasing and other techniques. The new approach is verified in a 40-nm CMOS technology by simulation. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/SOCC.2012.6398352 | SoCC |
Keywords | Field | DocType |
size 40 nm,equalizer precharge scheme,sram chips,low-power 6t-sram,tree address decoder,cmos technology,leakage path reduction,equalisers,6t-based sram architecture,hierarchical subblocks,cmos memory circuits,dynamic power dissipation,standby power dissipation | Equalizer,Leakage (electronics),Standby power,Computer science,Dissipation,CMOS,Static random-access memory,Real-time computing,Electronic engineering,Address decoder | Conference |
ISSN | ISBN | Citations |
2164-1676 | 978-1-4673-1294-3 | 3 |
PageRank | References | Authors |
0.53 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuan Ren | 1 | 3 | 0.53 |
| Michael Gansen | 2 | 3 | 0.53 |
| Tobias G. Noll | 3 | 199 | 37.51 |