Name
Abstract | ||
|---|---|---|
Dedicated low-power SRAMs have become a crucial part of numerous applications, but various capacities, wordlengths and operational modes make it hard for designers to determine the best SRAM architecture. Additionally, many low-power techniques like hierarchical bitlines with local sense amplifiers and energy-efficient periphery circuits are typically utilized but not supported by previously proposed power models. To solve these problems, a fast and accurate power estimation model is proposed for aiding low-power SRAM designs. It operates as a parameter optimization tool and precisely fits the customized SRAM circuit and architecture. Specifically, the model is based on two major SRAM components: the address decoder and the memory array. It is verified that the estimation error of the model is less than 10% compared to results based on time-hungry extracted netlist simulations in a 40-nm CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/VLSI-SoC.2013.6673266 | VLSI-SOC |
Keywords | Field | DocType |
optimisation,parameter quantitative optimization,parameter optimization tool,energy-efficient periphery circuits,hierarchical systems,power model,sram chips,memory array,low-power electronics,low-power sram,estimation theory,sram,hierarchical bitlines,address decoder,power estimation model,local sense amplifiers,sram architecture,low power electronics | Netlist,CMOS,Static random-access memory,Electronic engineering,Estimation theory,Engineering,Electronic circuit,Address decoder,Amplifier,Low-power electronics | Conference |
Citations | PageRank | References |
1 | 0.37 | 5 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuan Ren | 1 | 1 | 0.71 |
| Tobias G. Noll | 2 | 199 | 37.51 |