Paper Info
Title
Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers
Abstract
This paper presents the enhancement of an ASIP's floating point performance by coupling of a co-processor and adding of special instructions. Processor hardware modifications and subsequent adaptation of software development tools (e.g. assembler, linker and compiler) are described. Additionally, this work focuses on seamless integration of the co-processor to enable ease of use for the application development. Power consumption and silicon area of the co-processor can be reduced by choosing an application specific subset of functions. Hardware description files of ASIP and co-processor are used for functional verification and processing cycle determination. Area and power estimation of the overall architecture is presented for a 90 nm standard cell CMOS technology. Finally, a design space exploration of the presented architecture used in a satellite navigation receiver reveals efficient co-processor configurations.
Year
DOI
Venue
2007
10.1109/ASAP.2007.4429996
Montreal, Que.
Keywords
Field
DocType
CMOS integrated circuits,floating point arithmetic,formal verification,hardware description languages,program assemblers,program compilers,receivers,satellite navigation,ASIP floating point performance,CMOS technology,GNSS receivers,coprocessor architecture,functional verification,hardware description files,processing cycle determination,processor hardware modifications,satellite navigation receiver,software development tools
Functional verification,Satellite navigation,Computer science,Parallel computing,Compiler,Standard cell,Coprocessor,Application software,Design space exploration,Hardware description language,Embedded system
Conference
ISSN
ISBN
Citations 
2160-0511 E-ISBN : 978-1-4244-1027-9
978-1-4244-1027-9
2
PageRank 
References 
Authors
0.54
4
4
Name
Order
Citations
PageRank
Götz Kappen1153.50
el Bahri, S.220.54
Priebe, O.320.54
Tobias G. Noll419937.51