Name
Abstract | ||
|---|---|---|
Silicon technology continues to shrink, allowing a greater density of devices per unit area. At the same time, process and chip variations increase, making it more difficult to build power-efficient, functional chips. We first review the physical issues that are driving such increasing variation. Then, we look at state-of-the-art approaches to adapt to this variation. Voltage management is a key element, both in innovative management circuits, as well as in integration across the hardware/software design stack for adaptive control of the system. Leveraging error tolerance, where available, is as critical as building new memories that can avoid or mitigate sensitivity to variation. Finally, innovative models to predict the effects of variations are critical to guiding choices in the design process. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/ISSCC.2014.6757542 | Solid-State Circuits Conference Digest of Technical Papers |
DocType | ISSN | Citations |
Conference | 0193-6530 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eric Fluhr | 1 | 78 | 15.10 |
| mike polley | 2 | 0 | 0.34 |
| sehyun yang | 3 | 0 | 0.34 |
| Vasantha Erraguntla | 4 | 158 | 10.73 |
| Tobias G. Noll | 5 | 199 | 37.51 |
| Kees Van Berkel | 6 | 431 | 71.17 |