Paper Info
Title
High-level modeling and synthesis for embedded FPGAs
Abstract
The fast evolving applications in modern digital signal processing have an increasing demand for components which have high computational power and energy efficiency without compromising the flexibility. Embedded FPGA, which is the customized FPGA with heterogeneous fine-grained application specific operations and routing resources, has shown significantly improved efficiency in terms of throughput, power dissipation and chip area for the target application domain. On the other hand, the complexity of such architecture makes it difficult to perform an efficient architecture exploration and application synthesis without tool support. In this work, we propose a framework for the design of embedded FPGA (eFPGA) architectures, which is extended from an existing framework for Coarse-Grained Reconfigurable Architectures (CGRAs). The framework is composed of a high-level modeling formalism for eFPGAs to explore the mapping space, and a retargetable application synthesis flow. To enable fast design space exploration, a force-directed placement algorithm is proposed. Finally, we demonstrate the efficacy of this framework with demanding application kernels.
Year
DOI
Venue
2013
10.7873/DATE.2013.318
DATE
Keywords
Field
DocType
field programmable gate arrays,kernel,multiprocessor,computer architecture,solid modeling,routing,embedded systems
Digital signal processing,Computer architecture,Efficient energy use,Computer science,Field-programmable gate array,Chip,Multiprocessing,Real-time computing,Application domain,Throughput,Design space exploration,Embedded system
Conference
ISSN
Citations 
PageRank 
1530-1591
3
0.40
References 
Authors
12
7
Name
Order
Citations
PageRank
Xiaolin Chen1494.00
Shuai Li230.40
Jochen Schleifer351.12
Thomas Coenen451.12
Anupam Chattopadhyay531862.76
Gerd Ascheid61205144.76
Tobias G. Noll719937.51