LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates - Citegraph

Paper Info

Title
LDPC decoder area, timing, and energy models for early quantitative hardware cost estimates

Year	DOI	Keywords
2010	10.1109/ISSOC.2010.5625546	metals,decoding,routing,codecs,soc,silicon,costing,fir filter,integrated circuit design,system on chip,logic gates,cost estimation,high throughput
DocType	Citations	PageRank
Conference	8	0.77
References	Authors
2	2

Authors (2 rows)

Cited by (8 rows)

References (2 rows)

Name	Order	Citations	PageRank
matthias korb	1	8	0.77
Tobias G. Noll	2	199	37.51

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