Name
Abstract | ||
|---|---|---|
A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TVLSI.2008.2000323 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
line speed,weighted fair queueing,search tree,high-speed wfq packet scheduling,novel implementation,packet scheduler,internet protocol,next generation ip service,custom memory layout,scalable packet,130-nm silicon technology,queueing theory,scheduling,quality of service | Conference | 16 |
Issue | ISSN | ISBN |
7 | 1063-8210 | 0-7803-9782-7 |
Citations | PageRank | References |
5 | 0.43 | 14 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kieran McLaughlin | 1 | 208 | 22.19 |
| Sakir Sezer | 2 | 1010 | 84.22 |
| Holger Blume | 3 | 220 | 42.84 |
| Xin Yang | 4 | 22 | 4.91 |
| friederich kupzog | 5 | 5 | 0.43 |
| Tobias G. Noll | 6 | 199 | 37.51 |