Paper Info
Title
Architecture And Optimization Of Associative Memories Used For The Implementation Of Logic Functions Based On Nanoelectronic 1s1r Cells
Abstract
A neuromorphic architecture based on Binary Associative memories and nanoelectronic resistive switches is proposed for the realization of arbitrary logic/arithmetic functions. Subsets of non-trivial code sets based on error detecting 2-out-of-n-codes are thoroughly used to encode operands, results, and intermediate states in order to enhance the circuit reliability by mitigating the impact of device variability. 2-ary functions can be implemented by cascading a mixer memory, a correlator memory, and a response memory. By introduction of a new cost function based on class-specific word line-coverage, stochastic optimization is applied with the aim to minimize the overall number of active amplifiers. For various exemplary functions optimized architectures are compared against solutions obtained using a standard-cost function. It is especially shown that the consideration of word-line-coverage results in a significant circuit compaction.
Year
Venue
Keywords
2018
PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
Resistive Switches, Selector Device, Associative Memory, Clipped Hebbian Synaptic Rule, Reliability, logic functions, arithmetic function, nanoelectronics, BiNAM
Field
DocType
ISSN
Arithmetic function,Stochastic optimization,Associative property,Content-addressable memory,Computer science,Circuit reliability,Operand,Parallel computing,Neuromorphic engineering,Electronic engineering,Binary number
Conference
1530-1591
Citations 
PageRank 
References 
0
0.34
0
Authors
2
Name
Order
Citations
PageRank
Arne Heittmann1245.94
Tobias G. Noll219937.51