Name
Abstract | ||
|---|---|---|
A new error-tolerant finite impulse response (FIR) filter architecture for low-power high-performance applications is presented. The combination of low-cost residue coding and a novel structure, called modulo bitplane, proves to be very efficient Results for single-error correction of a typical 12-tap programmable FIR filter with 6-bit sample data and 8-bit coefficients show that it exhibits just 85% area overhead. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISCAS.2005.1465809 | ISCAS (5) |
Keywords | Field | DocType |
FIR filters,arithmetic codes,error correction codes,programmable filters,residue codes,6 bit,8 bit,CMOS,arithmetic codes,error-tolerant FIR filters,error-tolerant finite impulse response filter,low-cost residue codes,low-power FIR filters,modulo bitplane structure,multiple-tap programmable FIR filter,single-error correction | Digital signal processing,Modulo,Computer science,8-bit,CMOS,Electronic engineering,Redundancy (engineering),Fault tolerance,Throughput,Finite impulse response | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-8834-8 | 3 |
PageRank | References | Authors |
0.72 | 11 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| José L. Rodríguez-navarro | 1 | 3 | 0.72 |
| Michael Gansen | 2 | 3 | 0.72 |
| Tobias G. Noll | 3 | 199 | 37.51 |