Abstract | ||
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Quadratic-permutation-polynomial (QPP) interleavers are utilized in Turbo coding of the 4G-mobile-system LTE-Advanced due to the support of parallel, contention-free memory accesses. In principle, throughput rates of 1 Gbit/s can be supported with such interleavers in today's CMOS technologies. A systematic examination of the QPP interleaver properties has led to several design improvements concerning silicon area, energy per operation and the support of highly parallelized Turbo decoders. Regarding the interleaver network, it is proven that hardware-efficient butterfly and Bene?s networks can be applied with negligible configuration overhead. With respect to the interleaver address generation, we propose and analyze a recursive address calculation method. |
Year | DOI | Venue |
---|---|---|
2012 | 10.1109/ISSoC.2012.6376355 | System Chip |
Keywords | Field | DocType |
4G mobile communication,Long Term Evolution,VLSI,decoding,interleaved codes,turbo codes,4G-mobile-system LTE,CMOS technologies,LTE turbo decoders,QPP interleavers,VLSI architectures,bit rate 1 Gbit/s,parallel contention-free memory accesses,quadratic-permutation-polynomial interleavers,turbo coding | Turbo,Gigabit,Computer science,Parallel computing,Turbo code,Serial concatenated convolutional codes,CMOS,Theoretical computer science,Throughput,Decoding methods,Very-large-scale integration,Computer engineering | Conference |
ISBN | Citations | PageRank |
978-1-4673-2894-4 | 3 | 0.40 |
References | Authors | |
9 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Martin Broich | 1 | 3 | 0.40 |
Tobias G. Noll | 2 | 199 | 37.51 |