Name
Abstract | ||
|---|---|---|
In this paper a novel flexible architecture exemplarily applied for multioperable GNSS receivers including an ASIP and an arithmetic oriented embedded FPGA is presented. The advent of next generation GNSS-systems as well as different demands in different system phases require high flexibility. The proposed architecture provides high energy and area efficiency compared to software-programmable processor while preserving flexibility. Exemplarily the mapping of the computational intensive base band processing of a Navstar GPS receiver to an ASIP-eFPGA architecture will be discussed. Results are based on a standard cell based design regarding the ASIP. A design method for physically optimized VLSI-macros has been applied for the implementation of the eFPGA. All results are acquired for a 90 nm-CMOS technology. It will be shown that the proposed heterogeneous architecture features an attractive position in the design space regarding area and energy efficiency as well as flexibility. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1007/978-3-540-70550-5_15 | SAMOS |
Keywords | Field | DocType |
design method,energy efficient | Architecture,Baseband,Efficient energy use,Computer science,Field-programmable gate array,Real-time computing,Standard cell,Global Positioning System,GNSS applications,High energy | Conference |
Volume | ISSN | Citations |
5114 | 0302-9743 | 1 |
PageRank | References | Authors |
0.37 | 6 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Thorsten von Sydow | 1 | 1 | 0.37 |
| Holger Blume | 2 | 220 | 42.84 |
| Götz Kappen | 3 | 15 | 3.50 |
| Tobias G. Noll | 4 | 199 | 37.51 |