Paper Info
Title
A quantitative analysis of fixed-point LDPC-decoder implementations using hardware-accelerated HDL emulations
Abstract
Using hardware-accelerated HDL emulators of fixed-point implementations has several advantages in comparison to C-based simulations: The high degree of parallelism for example of field-programmable gate-array based hardware accelerators promise an increased emulation throughput. Furthermore, the HDL model of the considered circuit can be used in the following design process making an additional verification dispensable. For a system analysis of different low-density parity-check (LDPC) decoders such an emulator is practically inevitable from a throughput perspective: the outstanding error correction capability of those decoders allowing for bit-error rates (BER) of well below 10-10 requires a simulative decoding of billions of blocks. In this work, an HDL-based emulator is used. The designed HDL model is highly parameterizable and includes an LDPC decoder and high-quality Box-Muller-based white Gaussian-noise generators to create rare error-events. Using this emulator a comparison of the decoding capability of different fixed-point decoder implementations has been performed. Additionally, accurate cost-models are used for estimating the hardware costs of the different decoder implementations which enable an identification of Pareto-optimal decoder implementations. Finally, the achievable emulator throughput is discussed and compared to the simulation throughput of a speed optimized C-model.
Year
DOI
Venue
2012
10.1109/SAMOS.2012.6404189
Embedded Computer Systems
Keywords
Field
DocType
Gaussian noise,Pareto analysis,decoding,error correction codes,error statistics,field programmable gate arrays,hardware description languages,noise generators,parity check codes,BER,Pareto-optimal decoder implementations,cost-models,decoding capability,design process,error correction capability,field-programmable gate-array-based hardware accelerators,fixed-point LDPC- decoder implementations,fixed-point decoder implementations,hardware costs estimation,hardware-accelerated HDL emulations,high-quality box-Muller-based white Gaussian-noise generators,low-density parity-check decoders,optimized C-model speed,quantitative analysis,simulation throughput,simulative decoding,system analysis
Low-density parity-check code,Degree of parallelism,Computer science,Field-programmable gate array,Emulation,Soft-decision decoder,Decoding methods,Throughput,Computer hardware,Hardware description language
Conference
ISBN
Citations 
PageRank 
978-1-4673-2296-6
1
0.36
References 
Authors
10
2
Name
Order
Citations
PageRank
Matthias Korb110.36
Tobias G. Noll219937.51