Name
Abstract | ||
|---|---|---|
Field Programmable Gate Array Architectures (FPGA) are known to facilitate efficient implementations of signal processing algorithms. Their computational efficiency for arithmetic datapaths in terms of power and performance is typically ranked better than that of general purpose processors. This paper analyses the efficiency gain for MP3 decoding oil an FPGA. The results of ail exemplary FPGA implementation of a complete MP3 decoder featuring arithmetic datapaths as well as control overhead are compared concerning performance and power consumption to further implementation alternatives. Furthermore, the results are compared to requirements for a deployment in portable environments. |
Year | Venue | Keywords |
|---|---|---|
2007 | PARALLEL COMPUTING: ARCHITECTURES, ALGORITHMS AND APPLICATIONS | field programmable gate array,signal processing |
Field | DocType | Volume |
Permission,Computer science,Parallel computing,Citation,Programmable logic array,Simple programmable logic device,Notice,Computer hardware,Von Neumann architecture,Macrocell array | Conference | 15 |
ISSN | Citations | PageRank |
0927-5452 | 0 | 0.34 |
References | Authors | |
3 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin Botteck | 1 | 59 | 5.02 |
| Holger Blume | 2 | 220 | 42.84 |
| Jörg Von Livonius | 3 | 12 | 1.93 |
| Martin Neuenhahn | 4 | 0 | 1.01 |
| Tobias G. Noll | 5 | 199 | 37.51 |