Name
Abstract | ||
|---|---|---|
A multi-mode Secure Hashing Algorithm (SHA) accelerator is fabricated in 45nm CMOS and occupies 0.0625mm2 with 18Gbps throughput and total power consumption of 50mW. The reconfigurable hardware accelerator computes SHA-1/224/256/384/512 message-digest using unified SHA bit-slices and configurable compression circuits resulting in 40% area reduction and <;3% performance overhead for reconfiguration with 23Gbps peak throughput in SHA-224/256 modes. SHA frequency ranges from 21MHz-1.8GHz across 320mV-1.35V supply voltage range. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ESSCIRC.2010.5619892 | Seville |
Keywords | DocType | ISSN |
cmos integrated circuits,cryptography,microprocessor chips,reconfigurable architectures,cmos,area reduction,bit rate 18 gbit/s,frequency 21 mhz to 1.8 ghz,message-digest,microprocessor,multimode secure hashing algorithm accelerator,power 50 mw,reconfigurable hardware accelerator,reconfigurable multimode sha hashing accelerator,size 45 nm,voltage 320 mv to 1.35 v,adders,reconfigurable hardware,registers,secure hash algorithm,hardware,throughput,message digest | Conference | 1930-8833 |
ISBN | Citations | PageRank |
978-1-4244-6662-7 | 5 | 0.55 |
References | Authors | |
6 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| rajaraman ramanarayanan | 1 | 5 | 0.55 |
| S. Mathew | 2 | 462 | 76.59 |
| farhana sheikh | 3 | 5 | 0.55 |
| suresh srinivasan | 4 | 5 | 0.55 |
| amit agarwal | 5 | 6 | 1.24 |
| S. K. Hsu | 6 | 521 | 52.06 |
| Himanshu Kaul | 7 | 456 | 51.07 |
| Mark A. Anders | 8 | 185 | 17.43 |
| Vasantha Erraguntla | 9 | 158 | 10.73 |
| Ram Krishnamurthy | 10 | 650 | 74.63 |